To improve the performance of radio-frequency, analog, or mixed-signal circuits, engineers often use techniques know as interleaving and pipelining. Interleaving is a technique that allows a signal to be processed in multiple parallel pathways at successive instants in time. Pipelining is a technique that allows a signal to be processed multiple times serially at successive instants in time. Both techniques allow multiple circuit elements to operate on a single analog signal, thereby improving the processing performance of the circuit. Performance in this context might mean, for example increasing the speed or resolution (where resolution is equivalent to dynamic range) of the circuit.
FIG. 1 is a block diagram of a time-interleaved system 10. A number, M, of typically identical processing elements 12-1, 12-2, 12-3, . . . ,12-M are configured to operate at a rate of 1/M times a circuit sampling rate Fs. Interleaving divides the frequency of a full-rate clock by a factor M and synthesizes M phased lower-speed sampling clocks 16-1, 16-2, 16-3, . . . ,16-M. The phases of successive lower-speed clocks are typically offset by Φ=360°/M, thereby forming equally spaced sampling instants of rates Fs/M. An optional combining operation 18 may then be used to combine the sampled signals. Such a combining operation might comprise adding or multiplexing, or may comprise a more complex operation such as filtering or averaging.
FIG. 2 is a block diagram of a pipelined system 20 that is capable of processing an input signal into one or more output signals. A signal is received at input node 22 and sequentially processed by M processing elements 24-1, 24-2, 24-3, . . . ,24-M. Processing elements 24-1, 24-2, 24-3, . . . ,24-M have associated inputs 26-1, 26-2, 26-3, . . . ,26-M and associated outputs 28-1, 28-2, 28-3, . . . ,28-M, each output of which is cascaded into a next element's input. Optional combinational outputs 30-1, 30-2, 30-3, . . . ,30-M may also be coupled to a combining operation 32, which may have additional secondary inputs 34. Pipelined system 20 may also have one or more feedback or feedforward loops and may output one or more outputs at output node 35.
Ideally, each of the nominally identical subsystem pathways in time-interleaved and pipelined systems have identical gain, offset, signal delay, clock timing, frequency response, and transfer function. In practice, however, no two circuit elements are the same. For example, in integrated circuit implementations of such systems, device-to-device mismatches are the result of process and temperature gradients. Such mismatches are problematic as they can result in subsystem pathways not having identical gain, offset, signal delay, clock timing, frequency response, and/or transfer function. Consequently, regardless of how well the individual processing elements perform on their own, errors can result in time-interleaved and pipelelined systems due to device-to-device mismatches. Such errors occur irrespective of whether the system is time-sampled or continuous, and regardless of whether the processing elements are arranged in parallel (as in the time-interleaved system shown in FIG. 1) or serially (as in the pipelined system shown in FIG. 2). Accordingly, device mismatch is a major concern, and it must be addressed and minimized if the benefits of time-interleaving and pipelining are to be exploited.
A number of solutions have been proposed to address mismatch of transistors in integrated circuits. Some of these approaches, which may or may not be useful in reducing device mismatch in time-interleaved and pipelined systems, include using large transistors, using lasers to trim resistors or fuses, and using capacitors to dynamically match devices in response to on-chip error signals. Unfortunately, each of these approaches has significant disadvantages. For instance, large transistors require large currents to operate at high speeds, consume large silicon area and power, and do not compensate for temperature or aging errors. Similarly, laser-trimming resistors or fuses necessitates use of large resistors or fuses, requires time-consuming laboratory trimming, and again does not compensate for temperature or aging errors. Finally, using capacitors to dynamically trim circuit elements requires wideband error-feedback loops and frequent updates, because on-chip capacitors leak due to the thermal generation of carriers in pn junctions.